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greenpak tm ? pcie rtd3 slg7nt41 31 silego technology, inc. rev 0 . 20 slg 7nt 4 1 31 _ds_r 0 2 0 preliminary revised november 2 6 , 201 2 slg 7nt 4 1 31 _gp_r0 0 3 general description silego greenpak slg 7nt 4 1 31 is a low power and small form device. the soc is housed in a 2mm x 2mm tdfn package which is optimal for using with small devices. features ? low power consumption ? 3.3v supply ? pb - free / rohs compliant ? halogen - free ? tdfn - 8 package pin configuration 1 2 3 4 8 7 6 5 vdd pwr_cntrl_gpio# plt_rst# device_wake# pcie_wake # device_reset# wake_gpio gnd tdfn - 8 top view thermal pad connected to gnd output summary ? 1 output C open drain ? 1 output C push - pull ? 1 output C 3 - state
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 2 2 block diagram
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 3 3 pin configuration pin # pin name type pin description 1 vdd power 3.3v supply voltage 2 pwr_cntrl_gpio# input digital input 3 plt _rst# input digital input 4 device_wake# input/ output 3 - state 5 gnd gnd ground 6 wake_gpio output open drain 7 pcie_wake# input/ output 3 - state 8 device_reset# out put push - pull exposed bottom pad gnd gnd ground ordering options & configuration part numb er package type slg7nt4 131 v v = tdfn - 8 slg7nt4 131 vtr vtr = tdfn - 8 C tape and reel (3k units)
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 4 4 absolute maximum ratings parameter min. max. unit v dd to gnd - 0.3 4.6 v voltage at input pins - 0.3 4.6 v current at input pin - 1.0 1.0 ma storage temperatu re range - 65 150 c junction temperature -- 150 c electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i q quiescent current static inputs and outputs -- 0.5 -- a t a operating temperature - 40 25 85 c v ih high - level input voltage logic input 1. 7 -- -- v v il low - level input voltage logic input -- -- 0. 95 v i ih high - level input leakage current logic input pins; v in =3.3v - 100 -- 100 na i il low - level input leak age current logic input pins; v in =0v - 100 -- 100 na t dly0 delay0 time 2 . 1 3 3 .9 m s v o h high - level output voltage push pull /3 - state o e=1 output logic high output level , i o h =8 m a 2. 4 -- -- v v ol output voltage low push pull /3 - state oe=1 output logic low output level, i o l = 8 m a -- -- 0. 4 v open drain, i ol = 20 ma -- -- 0. 4 v o maximal voltage applied to any pin in high - impedance state -- -- vdd v i oh high - level output current push pull /3 - state oe=1 output curren t, v o h = 2 . 4 v -- -- 8 ma i ol low - level output current push pull /3 - state oe=1 output current, v ol =0.4v 8 -- -- ma open drain, v ol = 0.4v 20 -- -- t stup start up time after vdd reaches 1.4v level -- 7 -- ms
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 5 5 timing diagram
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 6 6 slg 7nt 4 1 31 functionality waveform channel 1 (yellow/top line) C pin 2 ( pwr_cntrl_gpio# ) channel 2 ( blue/2nd line) C pin 3 ( plt_rst# ) channel 3 (magenta / bottom line ) C pin 8 ( device_reset# ) 1. device_reset# operation channel 1 (yellow/top line) C pin 2 ( pwr_cntrl_gpio # ) channel 2 ( light blue /2nd line) C pin 3 ( plt_rst# ) channel 3 (magenta / 3 nd line) C pin 4 ( device_wake# ) with external 10 k ? pull up resistors channel 3 ( blue /bottom line) C pin 3 ( pcie_wake# ) with external 10 k ? pull up resistors 2 . bi - directional f un ction
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 7 7 channel 1 (yellow/top line) C pin 2 ( pwr_cntrl_gpio # ) channel 2 ( light blue /2nd line) C pin 3 ( plt_rst# ) channel 3 (magenta / 3 nd line) C pin 4 ( device_wake# ) with external 10 k ? pull up resistors channel 3 ( blue /bottom line) C pin 9 ( wak e_gpio ) with external 10 k ? pull up resistors 3. mux function
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 8 8 package top marking datasheet revision programming code number part code revision date 0. 2 0 0 3 11/ 2 6 /2012
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 9 9 package drawing and dimensions tdfn - 8 package jedec mo - 229, variation wccd
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 10 10 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch tdfn 8l 2x2mm green 8 2x2x0.75 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w tdfn 8l 2x2mm green 2.3 2.3 1.05 4 4 1.55 1.75 3.5 8 recommended reflow soldering profile please s ee ipc/jedec j - std - 020: latest revision for reflow profile based on package volume of 3.00 mm 3 (nominal). more information can be found at www.jedec.org .
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 11 11 datasheet revision history date version change 1 1 / 0 8 /2012 0.1 new design 11/22/2012 0.11 changed input pins type to digital input 11/26/2012 0.20 c hanged device_wake # a n d pcie_wake # functionality to bi - directiona l
pcie rtd3 slg 7nt 4 1 31 slg 7nt4 1 31 _ds_ r 0 2 0 preliminary page 12 12 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this websi te is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.c om/ products are also available for purchase directly from silego at the silego online store at http://store.silego.com/ . silego technical support datasheets and errata, application notes and example designs, us er guides, and hardware support documents and the latest software releases are available at the silego website or can be requested directly at info@silego.com . for specific greenpak design or applications questions a nd support please send email requests to greenpak@silego.com users of silego products can receive assistance through several channels: online live support silego technology has live video technical assistance a nd sales support available at http://www.silego.com/ . please ask our live web receptionist to schedule a 1 on 1 training session with one of our application engineer s. contact your local sales representative custome rs can contact their local sales representative or field application engineer (fae) for support. loc al sales offices are also available to help customers. more information regarding your local representative is availa ble at the silego website or send a req uest to info@silego.com contact silego directly silego can be contacted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminars and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does no t assume any liability arising out of such applications or uses of its products. silego technology reserves the right to improve product design, functions and reliability without notice.

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